This invention relates to a memory cell structure integrated on a semiconductor, usable for either a volatile memory, such as a DRAM (Dynamic Random Access Memory) or a non-volatile memory, such as an EPROM, EEPROM (Electrically Erasable Programmable Read-Only Memory), or Flash EEPROM.
More particularly, the present invention relates to a memory cell of the type which comprises a capacitor having the first electrode and the second electrode separated by a dielectric layer. The invention further relates to a method of storing information into a memory cell which comprises a capacitor having the first electrode and the second electrode separated by a dielectric layer.
As it is known, the manufacture of semiconductor-integrated electronic memory devices is concerned with both volatile and non-volatile memories. The structures of non-volatile memory cells, such as cells of the EPROM, EEPROM and Flash EEPROM type, as well as the one of volatile memory cells, such as cells of the RAM and DRAM type, has been known for a long time. As an example, it is reminded that non-volatile EEPROMs require no refresh pulses, as do instead the charge-storing capacitive elements of the conventional volatile memory cells such as DRAMs.
In literature several methods of manufacturing EEPROMs are known, see for example the U.S. Pat. No. 3,649,884 (granted on Mar. 14, 1972 to Haneta and assigned to NEC) and the U.S. Pat. No. 4,870,470 (granted on Sep. 26, 1989 to Bass et al. and assigned to IBM).
The former of these documents discloses a field-effect transistor with a gate which includes a layer of Silicon-Rich Oxide (SRO) and in which it is injected a charge obtained from a silicon substrate, through a stoichiometric silicon oxide layer.
The latter document discloses a non-conductive structure wherein the charge is trapped and which is based on an injection of hot carriers from the control gate. More particularly, in this document it is described a cell structure which is formed as a stack comprising a layer of silicon-rich silicon nitride which serves as a floating gate; a dielectric layer acting as a barrier; and a second layer of silicon-rich silicon nitride which serves as a control gate.
The cell operation is based on a charge trapping injection mechanism. The silicon content of the two silicon-rich silicon nitride layers is controlled so that the first layer provides with an appreciable charge storage, but not with a significant charge conduction, and the second layer provides with an appreciable charge conductance, but not with a significant chargestorage. Thus, the charge is injected from the control gate into the floating gate and becomes trapped in the latter.
However, these memory cells have considerable disadvantages, foremost among which is the possible damage of the tunnel oxide each time that information is stored into the cell. Furthermore, the operating speed is drastically limited. Because of these reasons, EEPROMs cannot be used as the main memory of a computer.
On the other hand, non-volatile memory cells, such as DRAMs, are much faster and more compact. In currently manufactured DRAMs the elementary cell typically consists of a MOS (Metal Oxide Semiconductor) capacitor in series with a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) transistor used to select the cell. The information stored in the cell is the state of the MOS capacitor, which can be either in a depleted condition corresponding to a high logic level xe2x80x9cUPxe2x80x9d or in a opposite condition, corresponding to a low logic level xe2x80x9cDOWNxe2x80x9d. Since the fully depleted condition is metastable, the logic level xe2x80x9cUPxe2x80x9d tends to decline into the logic level xe2x80x9cDOWNxe2x80x9d, and this is an effect mainly due to a leakage current of the selection MOSFET. To prevent this decline from the level xe2x80x9cUPxe2x80x9d to the level xe2x80x9cDOWNxe2x80x9d, the information stored in the MOS capacitor is periodically xe2x80x9crefreshedxe2x80x9d with a regular frequency, which is on the order of a few kHz in present DRAM technology.
With an ever greater circuit density, the number of cells integrated on a single DRAM chip has increased, and the size of the individual capacitors decreased. This makes retaining a sufficient charge within the capacitor to provide an acceptable signal/noise ratio rather difficult. In addition, because of leakage currents, these volatile memory cells require ever more frequent refresh cycles to maintain their charge level, also following to the fact that their content gets lost as soon as the supply voltage is switched off or disconnected.
Thus, in the electronic industry there is the need to look for new methods of increasing storage capacity and refresh time, that is to form non-volatile DRAMs. An attempt has been made in this direction in the European Patent Application No. EP 0,557,581, proposing a single-transistor DRAM cell which comprises a tunnel oxide or a dual electron injector structure disposed between a charge build-up point and the floating gate in order to maintain the information also during the voltage interruptions.
However, the structure described in the above document is an expanded one and, accordingly, lacks scalability from the planar standpoint.
The new technical problem that underlies this invention is to contrive a memory cell structure for implementing volatile and non-volatile memory devices, which are scalable from the planar standpoint and fast at low costs, as well as a new method of storing information into the memory cell.
The resolution idea on which the present invention is based, is that of providing a cell structure, which allows to store information, by trapping the charge permanently within a semi-insulating material, and by shifting such charge reversibly between two different spatial positions corresponding to two logic levels xe2x80x9cUPxe2x80x9d and xe2x80x9cDOWNxe2x80x9d. The low mobility of the charge within the semi-insulating material guarantees a very long refresh time.
Based on such resolutive idea, the technical problem is solved by a memory cell of the type previously indicated and defined by the characterising portion of the enclosed claim 1.
The features and advantages of the memory cell according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.